library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use WORK.constants.all;

entity COPROCESSOR is
	port (
		-- Systesms signals
		clk : in std_logic;
		rst : in std_logic;
		
		-- Input from coming from the processor
		data_in		:	in std_logic_vector(DATA_SIZE-1 downto 0);
		addr		:	in std_logic_vector(ADDR_SIZE-1 downto 0);
		rd_en		:	in std_logic;
		wr_en		:	in std_logic;
		
		-- Output signals going to the processor
		data_out	:	out std_logic_vector(DATA_SIZE-1 downto 0);
		req_irq		:	out std_logic
		);
end COPROCESSOR;

architecture RTL of COPROCESSOR is 
		signal s_shift		:	std_logic;
		signal s_capture	:	std_logic;
		signal s_update	:	std_logic;

		signal s_gwen		:	std_logic;
		signal s_tdi		:	std_logic;
		signal s_tdo		:	std_logic;
		signal s_gw_reset	:	std_logic;
		signal s_hw_and_sw_reset 	:  std_logic;
	
	component CORE_LEFT
	port (
		-- Systesm signals
		clk			: in std_logic;
		reset		: in std_logic;
		
		-- Input from coming from the processor
		data_in		:	in std_logic_vector(DATA_SIZE-1 downto 0);
		addr		:	in std_logic_vector(ADDR_SIZE-1 downto 0);
		rd_en		:	in std_logic;
		wr_en		:	in std_logic;
		
		-- Output signals going to the processor
		data_out	:	out std_logic_vector(DATA_SIZE-1 downto 0);
		req_irq		:	out std_logic;
		
		-- Output signals going to the monitoring chain : Core_Right
		shift		:	out std_logic;
		capture		:	out std_logic;
		update		:	out std_logic;
		gwen		:	out std_logic;
		gw_reset		:	out std_logic;
		hw_and_sw_reset : out std_logic;
		tdi			:	out std_logic;
		-- Input signal coming from the monitoring chain
		tdo			:	in std_logic
		);
end component;

component CORE_RIGHT
	port (
		-- Systesm signals
		clk			: in std_logic;
		
		-- Input signals coming from Core_Left
		shift		:	in std_logic;
		capture		:	in std_logic;
		update		:	in std_logic;
		gwen		:	in std_logic;
		gw_reset		:	in std_logic;
		hw_and_sw_reset : in std_logic;
		tdi			:	in std_logic;
		-- Output signal going to Core_Left
		tdo			:	out std_logic
	);
end component;

begin
    -- purpose: CORE LEFT - CONTROL UNIT
    -- type   : structural
	COPRO_LEFT :
		core_left
		port map(
			clk			=> clk,
			reset		=> rst,
			addr		=> addr,
			rd_en		=> rd_en,
			wr_en		=> wr_en,
			data_in 	=> data_in,
			data_out	=> data_out,
			req_irq		=> req_irq,
			
			shift		=> s_shift,
			capture		=> s_capture,
			update 		=> s_update,
			gwen		=> s_gwen,
			gw_reset		=> s_gw_reset,
			hw_and_sw_reset => s_hw_and_sw_reset,
			tdi			=> s_tdi,
			tdo			=> s_tdo
		);
		
	-- purpose: Core_Right - Implementation of gateways and monitored components
	-- type   : Structural
	COPRO_RIGHT :
		core_right
		port map(
			clk			=> clk,
			shift		=> s_shift,
			capture		=> s_capture,
			update 		=> s_update,
			gwen		=> s_gwen,
			gw_reset		=> s_gw_reset,
			hw_and_sw_reset => s_hw_and_sw_reset,
			tdi			=> s_tdi,
			tdo			=> s_tdo	
		);
end;
